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philips semiconductors product specification n-channel trenchmos ? transistor phb11n03lt, PHD11N03LT logic level fet features symbol quick reference data ? 'trench' technology v dss = 30 v ? low on-state resistance ? fast switching i d = 10.5 a ? logic level compatible r ds(on) 150 m w (v gs = 5 v) r ds(on) 130 m w (v gs = 10 v) general description n-channel enhancement mode, logic level, field-effect power transistor in a plastic envelope using ' trench ' technology. applications:- ? d.c. to d.c. converters ? switched mode power supplies the phb11n03lt is supplied in the sot404 (d 2 pak) surface mounting package. the PHD11N03LT is supplied in the sot428 (dpak) surface mounting package. pinning sot428 (dpak) sot404 (d 2 pak) pin description 1 gate 2 drain 1 3 source tab drain limiting values limiting values in accordance with the absolute maximum system (iec 134) symbol parameter conditions min. max. unit v dss drain-source voltage t j = 25 ?c to 175?c - 30 v v dgr drain-gate voltage t j = 25 ?c to 175?c; r gs = 20 k w -30v v gs gate-source voltage - 15 v v gsm pulsed gate-source voltage - 20 v i d continuous drain current t mb = 25 ?c - 10.3 a t mb = 100 ?c - 7.3 a i dm pulsed drain current t mb = 25 ?c - 41 a p d total power dissipation t mb = 25 ?c - 33 w t j , t stg operating junction and - 55 175 ?c storage temperature d g s 13 tab 2 1 2 3 tab 1 it is not possible to make contact to pin 2 of the sot404 or sot428 package september 1999 1 rev 1.000
philips semiconductors product specification n-channel trenchmos ? transistor phb11n03lt, PHD11N03LT logic level fet avalanche energy limiting values limiting values in accordance with the absolute maximum system (iec 134) symbol parameter conditions min. max. unit e as non-repetitive avalanche unclamped inductive load, i as = 3.3 a; - 25 mj energy t p = 220 m s; t j prior to avalanche = 25?c; v dd 15 v; r gs = 50 w ; v gs = 5 v; refer to fig:15 i as peak non-repetitive - 10.3 a avalanche current thermal resistances symbol parameter conditions typ. max. unit r th j-mb thermal resistance junction - 4.5 k/w to mounting base r th j-a thermal resistance junction sot428 and sot404 package, pcb 50 - k/w to ambient mounted, minimum footprint electrical characteristics t j = 25?c unless otherwise specified symbol parameter conditions min. typ. max. unit v (br)dss drain-source breakdown v gs = 0 v; i d = 0.25 ma; 30 - - v voltage t j = -55?c 26 - - v v gs(to) gate threshold voltage v ds = v gs ; i d = 1 ma 1.0 1.5 2.0 v t j = 175?c 0.5 - - v t j = -55?c - - 2.3 v r ds(on) drain-source on-state v gs = 10 v; i d = 5.5 a - 100 130 m w resistance v gs = 5 v; i d = 5.5 a - 120 150 m w t j = 175?c - 250 315 m w g fs forward transconductance v ds = 25 v; i d = 5.5 a 4 7 - s i gss gate source leakage current v gs = 5 v; v ds = 0 v - 10 100 na i dss zero gate voltage drain v ds = 30 v; v gs = 0 v; - 0.05 10 m a current t j = 175?c - - 500 m a q g(tot) total gate charge i d = 10 a; v dd = 15 v; v gs = 5 v - 3.8 - nc q gs gate-source charge - 1.2 - nc q gd gate-drain (miller) charge - 1.7 - nc t d on turn-on delay time v dd = 30 v; r d = 2.7 w ;-616ns t r turn-on rise time r g = 10 w ; v gs = 5 v - 64 80 ns t d off turn-off delay time resistive load - 20 30 ns t f turn-off fall time - 26 40 ns l d internal drain inductance measured from tab to centre of die - 3.5 - nh l d internal drain inductance measured from drain lead to centre of die - 4.5 - nh (sot78 package only) l s internal source inductance measured from source lead to source - 7.5 - nh bond pad c iss input capacitance v gs = 0 v; v ds = 25 v; f = 1 mhz - 250 330 pf c oss output capacitance - 55 75 pf c rss feedback capacitance - 42 55 pf september 1999 2 rev 1.000
philips semiconductors product specification n-channel trenchmos ? transistor phb11n03lt, PHD11N03LT logic level fet reverse diode limiting values and characteristics t j = 25?c unless otherwise specified symbol parameter conditions min. typ. max. unit i s continuous source current - - 10.3 a (body diode) i sm pulsed source current (body - - 41 a diode) v sd diode forward voltage i f = 10 a; v gs = 0 v - 1.15 1.5 v t rr reverse recovery time i f = 10 a; -di f /dt = 100 a/ m s; - 35 - ns q rr reverse recovery charge v gs = 0 v; v r = 30 v - 55 - nc september 1999 3 rev 1.000
philips semiconductors product specification n-channel trenchmos ? transistor phb11n03lt, PHD11N03LT logic level fet fig.1. normalised power dissipation. pd% = 100 p d /p d 25 ?c = f(t mb ) fig.2. normalised continuous drain current. id% = 100 i d /i d 25 ?c = f(t mb ); conditions: v gs 3 5 v fig.3. safe operating area. t mb = 25 ?c i d & i dm = f(v ds ); i dm single pulse; parameter t p fig.4. transient thermal impedance. z th j-mb = f(t); parameter d = t p /t fig.5. typical output characteristics, t j = 25 ?c . i d = f(v ds ) fig.6. typical on-state resistance, t j = 25 ?c . r ds(on) = f(i d ) normalised power derating, pd (%) 0 10 20 30 40 50 60 70 80 90 100 0 25 50 75 100 125 150 175 mounting base temperature, tmb (c) 0.1 1 10 1e-06 1e-05 1e-04 1e-03 1e-02 1e-01 1e+00 pulse width, tp (s) transient thermal impedance, zth j-mb (k/w) single pulse d = 0.5 0.2 0.1 0.05 0.02 tp d = tp/t d p t normalised current derating, id (%) 0 10 20 30 40 50 60 70 80 90 100 0 25 50 75 100 125 150 175 mounting base temperature, tmb (c) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 drain-source voltage, vds (v) drain current, id (a) 2.8 v tj = 25 c vgs = 10v 3 v 3.2 v 3.4 v 2.4 v 5 v 2.6 v 0.1 1 10 100 1 10 100 drain-source voltage, vds (v) peak pulsed drain current, idm (a) d.c. 100 ms 10 ms rds(on) = vds/ id 1 ms tp = 10 us 100 us 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 01234567891011 drain current, id (a) drain-source on resistance, rds(on) (ohms) vgs = 10v tj = 25 c 3.2 v 5 v 3.4 v 3 v 2.8v 2.6 v 2.4 v september 1999 4 rev 1.000
philips semiconductors product specification n-channel trenchmos ? transistor phb11n03lt, PHD11N03LT logic level fet fig.7. typical transfer characteristics. i d = f(v gs ) fig.8. typical transconductance, t j = 25 ?c . g fs = f(i d ) fig.9. normalised drain-source on-state resistance. r ds(on) /r ds(on)25 ?c = f(t j ) fig.10. gate threshold voltage. v gs(to) = f(t j ); conditions: i d = 1 ma; v ds = v gs fig.11. sub-threshold drain current. i d = f(v gs) ; conditions: t j = 25 ?c; v ds = v gs fig.12. typical capacitances, c iss , c oss , c rss . c = f(v ds ); conditions: v gs = 0 v; f = 1 mhz 0 1 2 3 4 5 6 7 8 9 10 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 gate-source voltage, vgs (v) drain current, id (a) vds > id x rds(on) tj = 25 c 175 c threshold voltage, vgs(to) (v) 0 0.25 0.5 0.75 1 1.25 1.5 1.75 2 2.25 -60 -40 -20 0 20 40 60 80 100 120 140 160 180 junction temperature, tj (c) typical maximum minimum 0 1 2 3 4 5 6 7 8 012345678910 drain current, id (a) transconductance, gfs (s) tj = 25 c 175 c vds > id x rds(on) drain current, id (a) 1.0e-06 1.0e-05 1.0e-04 1.0e-03 1.0e-02 1.0e-01 0 0.5 1 1.5 2 2.5 3 gate-source voltage, vgs (v) minimum typical maximum normalised on-state resistance 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 2.2 2.4 -60 -40 -20 0 20 40 60 80 100 120 140 160 180 junction temperature, tj (c) 10 100 1000 0.1 1 10 100 drain-source voltage, vds (v) capacitances, ciss, coss, crss (pf) ciss coss crss september 1999 5 rev 1.000
philips semiconductors product specification n-channel trenchmos ? transistor phb11n03lt, PHD11N03LT logic level fet fig.13. typical turn-on gate-charge characteristics. v gs = f(q g ) fig.14. typical reverse diode current. i f = f(v sds ); conditions: v gs = 0 v; parameter t j fig.15. maximum permissible non-repetitive avalanche current (i as ) versus avalanche time (t av ); unclamped inductive load 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 012345678910 gate charge, qg (nc) gate-source voltage, vgs (v) id = 10a tj = 25 c vdd = 15 v 0.1 1 10 100 0.001 0.01 0.1 1 10 avalanche time, t av (ms) maximum avalanche current, i as (a) tj prior to avalanche = 150 c 25 c 0 1 2 3 4 5 6 7 8 9 10 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 1.1 1.2 source-drain voltage, vsds (v) source-drain diode current, if (a) tj = 25 c 175 c vgs = 0 v september 1999 6 rev 1.000
philips semiconductors product specification n-channel trenchmos ? transistor phb11n03lt, PHD11N03LT logic level fet mechanical data fig.16. sot404 surface mounting package. centre pin connected to mounting base. notes 1. this product is supplied in anti-static packaging. the gate-source input must be protected against static discharge during transport or handling. 2. refer to smd footprint design and soldering guidelines, data handbook sc18. 3. epoxy meets ul94 v0 at 1/8". unit a references outline version european projection issue date iec jedec eiaj mm a 1 d 1 d max. e el p h d q c 2.54 2.60 2.20 15.40 14.80 2.90 2.10 11 1.60 1.20 10.30 9.70 4.50 4.10 1.40 1.27 0.85 0.60 0.64 0.46 b dimensions (mm are the original dimensions) sot404 0 2.5 5 mm scale plastic single-ended surface mounted package (philips version of d 2 -pak); 3 leads (one lead cropped) sot404 e e e b d 1 h d d q l p c a 1 a 13 2 mounting base 98-12-14 99-06-25 september 1999 7 rev 1.000
philips semiconductors product specification n-channel trenchmos ? transistor phb11n03lt, PHD11N03LT logic level fet mounting instructions dimensions in mm fig.17. sot404 : soldering pattern for surface mounting . 17.5 11.5 9.0 5.08 3.8 2.0 september 1999 8 rev 1.000
philips semiconductors product specification n-channel trenchmos ? transistor phb11n03lt, PHD11N03LT logic level fet mechanical data fig.18. sot428 surface mounting package. centre pin connected to mounting base. notes 1. this product is supplied in anti-static packaging. the gate-source input must be protected against static discharge during transport or handling. 2. refer to smd footprint design and soldering guidelines, data handbook sc18. 3. epoxy meets ul94 v0 at 1/8". references outline version european projection issue date iec jedec eiaj sot428 98-04-07 0 10 20 mm scale plastic single-ended surface mounted package (philips version of d-pak); 3 leads (one lead cropped) sot428 e b 2 d 1 wa m bc b 1 l 1 l 13 2 d e 1 h e l 2 note 1. measured from heatsink back to lead. e 1 e a a 2 a a 1 y seating plane mounting base a 1 (1) d max. b d 1 max. e max. h e max. w y max. a 2 b 2 b 1 max. c e 1 min. ee 1 l 1 min. l 2 l a max. unit dimensions (mm are the original dimensions) 0.2 0.2 mm 2.38 2.22 0.65 0.45 0.89 0.71 0.89 0.71 1.1 0.9 5.36 5.26 0.4 0.2 6.22 5.98 4.81 4.45 2.285 4.57 10.4 9.6 0.5 0.7 0.5 6.73 6.47 4.0 2.95 2.55 september 1999 9 rev 1.000
philips semiconductors product specification n-channel trenchmos ? transistor phb11n03lt, PHD11N03LT logic level fet mounting instructions dimensions in mm fig.19. sot428 : soldering pattern for surface mounting . 7.0 7.0 2.15 2.5 4.57 1.5 september 1999 10 rev 1.000
philips semiconductors product specification n-channel trenchmos ? transistor phb11n03lt, PHD11N03LT logic level fet definitions data sheet status objective specification this data sheet contains target or goal specifications for product development. preliminary specification this data sheet contains preliminary data; supplementary data may be published later. product specification this data sheet contains final product specifications. limiting values limiting values are given in accordance with the absolute maximum rating system (iec 134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the device at these or at any other conditions above those given in the characteristics sections of this specification is not implied. exposure to limiting values for extended periods may affect device reliability. application information where application information is given, it is advisory and does not form part of the specification. philips electronics n.v. 1999 all rights are reserved. reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. the information presented in this document does not form part of any quotation or contract, it is believed to be accurate and reliable and may be changed without notice. no liability will be accepted by the publisher for any consequence of its use. publication thereof does not convey nor imply any license under patent or other industrial or intellectual property rights. life support applications these products are not designed for use in life support appliances, devices or systems where malfunction of these products can be reasonably expected to result in personal injury. philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify philips for any damages resulting from such improper use or sale. september 1999 11 rev 1.000

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